1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a voltage generator generating an internal power voltage lower than an externally applied power voltage.
2. Description of the Related Art
Integration scale of semiconductor integrated circuits has been increased by reducing sizes of circuit elements such as transistors formed therein, and as a result of such reduction in sizes of circuit elements, large scale integrated circuits (LSI) and very large scale integrated circuit (VLSI) have been realized. For example, sizes of MOS field effect transistors, particularly channel length of MOS transistors in MOS dynamic memories (DRAMs) has been reduced in accordance with the increase of the memory capacities. For example, in the case of prototype 4 M-bit DRAMs which are recently announced by DRAM manufactures, MOS transistors having the channel length of 1 micron or less are employed.
However, if the MOS transistors having such short channel length as 1 micron or less are supplied with a conventional power voltage of 5 volts, the characteristics of the short-channel MOS transistors are likely to be degraded due to hot carriers. To prevent such degradation, so-called short-channel effect must be taken into consideration in designing ICs. For avoiding the troublesome consideration for the short-channel effect, it is desirable to employ a power voltage lower than 5 volts for driving the short-channel MOS transistors. In view of interface with the system outside the DRAMs and simplification of power voltage source, however, it is still advantageous to employ the conventional power voltage of 5 volts in common.
Under the above circumstance, it has been known to provide a voltage generator generating a power voltage lower than 5 volts from the conventional 5 volts power voltage in the same DRAM chip for driving memory section in which the short-channel MOS transistors are used. Thus, with keeping the unification of the power voltage with the peripheral system, the problems due to the short channel length of MOS transistors can be effectively solved by the proposal of using the internal voltage generator.
An example of the 4 M-bit DRAM employing the proposed internal voltage generator is shown in an article "A 4Mb DRAM with Half Internal-Voltage Bitline Precharge" 1986 IEEE International Solid-State Circuit Conference pp. 270-271.
In order to evaluate reliability of semiconductor integrated circuits such as DRAMS, the so-called acceleration test has been widely employed. The acceleration test is a test performed in a condition in which the power voltage and the atmospheric temperature are raised above the usual operating voltage (e.g. 5 volts) and the usual operating temperature (e.g. -10.degree. C. to 80.degree. C.), respectively. Under such accelerated condition, the semiconductor integrated circuits are laid under an operating condition for a certain period of time. Namely, the semiconductor memory circuits to be tested are laid under such sever operating condition that the faulty factors of the semiconductor integrated circuits are actualized in a short time period. Thus, the reliability can be examined in a short time period.
However, it is difficult to achieve the acceleration test for the semiconductor integrated circuit using the internal voltage generator. This is because the internal voltage generator generates the constant internal voltage irrespective of the power voltage applied thereto for the acceleration test. It is, therefore, impossible to raise the internal voltage applied to the short-channel MOS transistors in the integrated circuit to be tested. Thus, the usage of the internal voltage generator has a great problem for performing the acceleration test.